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(parent: 93de581) | patch
add litepcie core
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 17 Apr 2015 11:45:01 +0000 (13:45 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 17 Apr 2015 11:45:01 +0000 (13:45 +0200)
commitd22d58c7cc8997c0531c4e19d0c2069558024a35
treee0b93a0b3c1805531db00ed7d1f6cc0aea9e0bdftree
parent93de581931e9bb29f2e329258e665e74de1403dbcommit | diff
add litepcie core
43 files changed:
misoclib/com/litepcie/LICENSE [new file with mode: 0644] blob
misoclib/com/litepcie/README [new file with mode: 0644] blob
misoclib/com/litepcie/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/common.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/irq/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/irq/interrupt_controller.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/packet/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/packet/common.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/packet/depacketizer.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/packet/packetizer.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/switch/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/switch/arbiter.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/switch/common.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/switch/crossbar.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/switch/dispatcher.py [new file with mode: 0644] blob
misoclib/com/litepcie/core/switch/request_controller.py [new file with mode: 0644] blob
misoclib/com/litepcie/doc/.keep_me [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/build/.keep_me [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/make.py [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/targets/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/targets/dma.py [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/test/make.py [new file with mode: 0644] blob
misoclib/com/litepcie/example_designs/test/test_regs.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/bridge/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/bridge/wishbone.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/dma/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/dma/common.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/dma/reader.py [new file with mode: 0644] blob
misoclib/com/litepcie/frontend/dma/writer.py [new file with mode: 0644] blob
misoclib/com/litepcie/litepcie-version.txt [new file with mode: 0644] blob
misoclib/com/litepcie/phy/__init__.py [new file with mode: 0644] blob
misoclib/com/litepcie/phy/s7pciephy.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/Makefile [new file with mode: 0644] blob
misoclib/com/litepcie/test/common.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/dma_tb.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/model/chipset.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/model/host.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/model/phy.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/model/tlp.py [new file with mode: 0644] blob
misoclib/com/litepcie/test/wishbone_tb.py [new file with mode: 0644] blob