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(parent: 31ab997) | patch
Added basic tutorial for generating verilog, vcd, dot diagram
authorAndrey Miroshnikov <andrey@technepisteme.xyz>
Sun, 10 Oct 2021 10:54:32 +0000 (11:54 +0100)
committerAndrey Miroshnikov <andrey@technepisteme.xyz>
Sun, 10 Oct 2021 10:54:32 +0000 (11:54 +0100)
commitd2574c9f02f98145aa12612dec108c0c8aa290ca
tree8b22026d607dd71b3bcde97a1ae99acb6180d7fbtree
parent31ab9979144c53878405c14f23202f1b6975dfd6commit | diff
Added basic tutorial for generating verilog, vcd, dot diagram
docs/learning_nmigen.mdwn diff | blob | history
docs/nmigen_verilog_tb.png [new file with mode: 0644] blob
http://libre-riscv.org ikiwiki