examples/fir: print Verilog source
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Fri, 8 Jun 2012 12:00:49 +0000 (14:00 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Fri, 8 Jun 2012 12:00:49 +0000 (14:00 +0200)
commitd280723618b8a75c7f6a0d283c89b0fc43410af4
tree9c102c8f4b3a0db9b2308bfff6462af63005342f
parentb00e8fa826f14c067b70b630acd72d1d439bd0b8
examples/fir: print Verilog source
examples/fir.py