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(parent: 42daafb) | patch
hdl.mem: ensure transparent read port model has correct latency.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 13:01:08 +0000 (13:01 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 13:01:08 +0000 (13:01 +0000)
commitd2929611c7e46eac486056922dc4039795ac78fa
tree3b26f9a602fe7a8e62f1eb39c57de058745a7f7ctree
parent42daafbd04ad9ad8ec1b865adcc549bb18ee082bcommit | diff
hdl.mem: ensure transparent read port model has correct latency.
nmigen/hdl/mem.py diff | blob | history
nmigen/test/test_sim.py diff | blob | history