nv50/ir: implement mad post ra folding for nvc0+
authorKarol Herbst <karolherbst@gmail.com>
Sun, 26 Mar 2017 19:45:58 +0000 (21:45 +0200)
committerIlia Mirkin <imirkin@alum.mit.edu>
Sat, 1 Apr 2017 03:57:13 +0000 (23:57 -0400)
commitd346b8588c36949695f2b01ca76619e84754dd50
tree250fa91aa9921ac68e2d52b36afd8b689cc37b02
parentd6ce32514760296b19f7609ec12f25e46c8ea34a
nv50/ir: implement mad post ra folding for nvc0+

changes for GpuTest /test=pixmark_piano /benchmark /no_scorebox /msaa=0
/benchmark_duration_ms=60000 /width=1024 /height=640:

score: 1026 -> 1045

changes for shader-db:
total instructions in shared programs : 3943335 -> 3934925 (-0.21%)
total gprs used in shared programs    : 481563 -> 481563 (0.00%)
total local used in shared programs   : 27469 -> 27469 (0.00%)
total bytes used in shared programs   : 36139384 -> 36061888 (-0.21%)

                local        gpr       inst      bytes
    helped           0           0        3587        3587
      hurt           0           0           0           0

v2: removed TODO
    reorderd to show changes without RA modification
    removed stale debugging print() call
v3: remove predicate checks
    enable only for gf100 ISA

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp