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(merge: b783dbe 13117bb)
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
authorAhmed Irfan <ahmedirfan1983@gmail.com>
Mon, 22 Sep 2014 09:35:04 +0000 (11:35 +0200)
committerAhmed Irfan <ahmedirfan1983@gmail.com>
Mon, 22 Sep 2014 09:35:04 +0000 (11:35 +0200)
commitd3c67ad9b61f602de1100cd264efd227dcacb417
tree88c462c53bdab128cd1edbded42483772f82612atree
parentb783dbe148e6d246ebd107c0913de2989ab5af48commit | diff
parent13117bb346dd02d2345f716b4403239aebe3d0e2commit | diff
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
backends/btor/btor.cc
backends/btor/btor.cc diff1 | diff2 | blob | history
backends/btor/verilog2btor.sh diff1 | diff2 | blob | history