Merge pull request #1569 from YosysHQ/eddie/fix_1531
authorEddie Hung <eddie@fpgeh.com>
Thu, 19 Dec 2019 17:21:33 +0000 (12:21 -0500)
committerGitHub <noreply@github.com>
Thu, 19 Dec 2019 17:21:33 +0000 (12:21 -0500)
commitd406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c
tree29413acb3d172859516920d054bfddcdf0fec482
parentd675f22f4e4166ef2cd13f1a9a28f8bd35511539
parent1ac1697e15ff72e69f4dfbf6922f0871c81bdff2
Merge pull request #1569 from YosysHQ/eddie/fix_1531

verilog: preserve size of $genval$-s in for loops