Use read_args for read_verilog
authorEddie Hung <eddie@fpgeh.com>
Sat, 5 Oct 2019 00:27:05 +0000 (17:27 -0700)
committerEddie Hung <eddie@fpgeh.com>
Sat, 5 Oct 2019 00:27:05 +0000 (17:27 -0700)
commitd4212d128b5985cf09f5e7f14bc06e7323e644ac
tree2559c896b7cf787674e477feb3af4763cb6967f9
parent7959e9d6b25d7afefded4b14e14ccf2b0b5af553
Use read_args for read_verilog
techlibs/xilinx/synth_xilinx.cc