Add minimal support for PSL in VHDL via Verific
authorClifford Wolf <clifford@clifford.at>
Fri, 28 Jul 2017 15:37:09 +0000 (17:37 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 28 Jul 2017 15:39:49 +0000 (17:39 +0200)
commitd4b9602cbdf8ee952b396381dfc8c7ddd8f735db
tree8f626920c7414c7fe6a8d81d6d6200b05cfe2bbf
parent4cf890dac121dc977fc4507168b48e47aecf5c46
Add minimal support for PSL in VHDL via Verific
frontends/verific/verific.cc