aarch64: Tweak movti and movtf patterns

aarch64: Tweak movti and movtf patterns

movti lacked an way of zeroing an FPR, meaning that we'd do:

        mov     x0, 0
        mov     x1, 0
        fmov    d0, x0
        fmov    v0.d[1], x1

instead of just:

        movi    v0.2d, #0

movtf had the opposite problem for GPRs: we'd generate:

        movi    v0.2d, #0
        fmov    x0, d0
        fmov    x1, v0.d[1]

instead of just:

        mov     x0, 0
        mov     x1, 0

Also, there was an unnecessary earlyclobber on the GPR<-GPR movtf
alternative (but not the movti one).  The splitter handles overlap
correctly.

The TF splitter used aarch64_reg_or_imm, but the _imm part only
accepts integer constants, not floating-point ones.  The patch
changes it to nonmemory_operand instead.

gcc/
	* config/aarch64/aarch64.c (aarch64_split_128bit_move_p): Add a
	function comment.  Tighten check for FP moves.
	* config/aarch64/aarch64.md (*movti_aarch64): Add a w<-Z alternative.
	(*movtf_aarch64): Handle r<-Y like r<-r.  Remove unnecessary
	earlyclobber.  Change splitter predicate from aarch64_reg_or_imm
	to nonmemory_operand.

gcc/testsuite/
	* gcc.target/aarch64/movtf_1.c: New test.
	* gcc.target/aarch64/movti_1.c: Likewise.