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(parent: 4f21323) | patch
Add Digilent Nexys 4 DDR board.
authorNicolas Robin <13021796+nicolas-robin@users.noreply.github.com>
Wed, 15 Jan 2020 17:35:57 +0000 (18:35 +0100)
committerwhitequark <whitequark@whitequark.org>
Wed, 15 Jan 2020 17:35:57 +0000 (17:35 +0000)
commitd53687cdcfc13f38eb22fd2eee66aaeeac9773dc
tree773b31352dea9aafd61d0b3dc1ebcfe8849413f2tree
parent4f2132388157b8fa82677afc18ffc325e4a35b6bcommit | diff
Add Digilent Nexys 4 DDR board.
nmigen_boards/nexys4ddr.py [new file with mode: 0644] blob