git.libre-soc.org Git - gem5.git/commit

author	Nathan Binkert <binkertn@umich.edu>
	Tue, 6 Mar 2007 19:13:43 +0000 (11:13 -0800)
committer	Nathan Binkert <binkertn@umich.edu>
	Tue, 6 Mar 2007 19:13:43 +0000 (11:13 -0800)
commit	d55b25cde6d2c072885a2c468d209fb18d6628e6
tree	391c4e66a69818a95037a5f2adccb2e8e0c84648	tree
parent	f800fddcea850822efee031b9b904280639da4c6	commit \| diff

Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3

52 files changed:

configs/common/FSConfig.py		diff \| blob \| history
configs/common/Simulation.py		diff \| blob \| history
configs/example/fs.py		diff \| blob \| history
src/base/annotate.cc		diff \| blob \| history
src/base/misc.cc		diff \| blob \| history
src/base/pollevent.cc		diff \| blob \| history
src/base/pollevent.hh		diff \| blob \| history
src/base/trace.hh		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/o3/fetch_impl.hh		diff \| blob \| history
src/cpu/o3/inst_queue_impl.hh		diff \| blob \| history
src/cpu/ozone/inst_queue_impl.hh		diff \| blob \| history
src/cpu/pc_event.cc		diff \| blob \| history
src/cpu/static_inst.cc		diff \| blob \| history
src/dev/etherbus.cc		diff \| blob \| history
src/dev/etherdump.cc		diff \| blob \| history
src/dev/etherlink.cc		diff \| blob \| history
src/dev/ide_disk.cc		diff \| blob \| history
src/dev/pcidev.cc		diff \| blob \| history
src/kern/tru64/tru64.hh		diff \| blob \| history
src/mem/cache/cache_blk.hh		diff \| blob \| history
src/mem/cache/miss/mshr.cc		diff \| blob \| history
src/mem/cache/tags/iic.cc		diff \| blob \| history
src/mem/cache/tags/lru.cc		diff \| blob \| history
src/mem/cache/tags/split_lifo.cc		diff \| blob \| history
src/mem/cache/tags/split_lru.cc		diff \| blob \| history
src/mem/packet.hh		diff \| blob \| history
src/mem/request.hh		diff \| blob \| history
src/python/m5/__init__.py		diff \| blob \| history
src/python/m5/convert.py		diff \| blob \| history
src/python/m5/event.py	[new file with mode: 0644]	blob
src/python/m5/main.py		diff \| blob \| history
src/python/m5/objects/BaseCPU.py		diff \| blob \| history
src/python/m5/objects/PhysicalMemory.py		diff \| blob \| history
src/python/m5/objects/Root.py		diff \| blob \| history
src/python/m5/params.py		diff \| blob \| history
src/python/m5/ticks.py	[new file with mode: 0644]	blob
src/python/swig/core.i		diff \| blob \| history
src/python/swig/event.i		diff \| blob \| history
src/sim/builder.cc		diff \| blob \| history
src/sim/core.cc		diff \| blob \| history
src/sim/core.hh		diff \| blob \| history
src/sim/eventq.cc		diff \| blob \| history
src/sim/main.cc		diff \| blob \| history
src/sim/root.cc		diff \| blob \| history
src/sim/sim_events.cc		diff \| blob \| history
src/sim/sim_events.hh		diff \| blob \| history
tests/configs/t1000-simple-atomic.py		diff \| blob \| history
tests/configs/tsunami-simple-atomic-dual.py		diff \| blob \| history
tests/configs/tsunami-simple-atomic.py		diff \| blob \| history
tests/configs/tsunami-simple-timing-dual.py		diff \| blob \| history
tests/configs/tsunami-simple-timing.py		diff \| blob \| history

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