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(parent: a25f370) | patch
Basic test for checking correct synthesis of SystemVerilog interfaces
authorRuben Undheim <ruben.undheim@gmail.com>
Thu, 18 Oct 2018 19:27:04 +0000 (21:27 +0200)
committerRuben Undheim <ruben.undheim@gmail.com>
Thu, 18 Oct 2018 20:40:53 +0000 (22:40 +0200)
commitd5aac2650f9169b2b890854083c5502b84adf115
tree9a0ef937b730d4c0f7452b0ceedfb642c83908abtree
parenta25f370191707def4d50dd42e74dec4d097a6a22commit | diff
Basic test for checking correct synthesis of SystemVerilog interfaces
Makefile diff | blob | history
tests/simple/svinterface1.sv [deleted file] blob | history
tests/svinterfaces/run-test.sh [new file with mode: 0755] blob
tests/svinterfaces/runone.sh [new file with mode: 0755] blob
tests/svinterfaces/svinterface1.sv [new file with mode: 0644] blob
tests/svinterfaces/svinterface1_ref.v [new file with mode: 0644] blob
tests/svinterfaces/svinterface1_tb.v [new file with mode: 0644] blob