RISC-V: Optimize si to di zero-extend followed by left shift.

RISC-V: Optimize si to di zero-extend followed by left shift.

This is potentially a sequence of 3 shifts, we which optimize to a sequence
of 2 shifts.  This can happen when unsigned int is used for array indexing.

	gcc/
	* config/riscv/riscv.md (zero_extendsidi2_shifted): New.

	gcc/testsuite/
	* gcc.target/riscv/zero-extend-5.c: New.