update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
authorCole Poirier <colepoirier@gmail.com>
Wed, 4 Nov 2020 00:55:59 +0000 (16:55 -0800)
committerCole Poirier <colepoirier@gmail.com>
Wed, 4 Nov 2020 00:55:59 +0000 (16:55 -0800)
commitd5f65e25cdae7d55b415507a41a508e284441baf
tree63c77837d5bfe9c3d72d9f9a05bb0bb356fc2795
parent820696054fb74311067715e624781449b807d524
update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg