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(parent: 83f7e7a) | patch
mem: Add ExternalMaster and ExternalSlave ports
authorAndrew Bardsley <Andrew.Bardsley@arm.com>
Thu, 16 Oct 2014 09:49:56 +0000 (05:49 -0400)
committerAndrew Bardsley <Andrew.Bardsley@arm.com>
Thu, 16 Oct 2014 09:49:56 +0000 (05:49 -0400)
commitd6732895a5c2e81da47ada339b5d9269c02e5e8b
treec8f1f235e96e76946dde6b914a903b5dd74d170ctree
parent83f7e7afaf962a6f7967c3ace00a85c58508e2e9commit | diff
mem: Add ExternalMaster and ExternalSlave ports

This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.
src/mem/ExternalMaster.py [new file with mode: 0644] blob
src/mem/ExternalSlave.py [new file with mode: 0644] blob
src/mem/SConscript diff | blob | history
src/mem/external_master.cc [new file with mode: 0644] blob
src/mem/external_master.hh [new file with mode: 0644] blob
src/mem/external_slave.cc [new file with mode: 0644] blob
src/mem/external_slave.hh [new file with mode: 0644] blob