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(parent: 32c0f26) | patch
add 8 CSRs for registers and predication each
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 29 Sep 2018 02:49:49 +0000 (03:49 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 29 Sep 2018 02:49:49 +0000 (03:49 +0100)
commitd677c93750bfc705f408a801727dc735be39ec9d
tree904e9cf04bf725e97a3a1d3d9e64d32010d89c34tree
parent32c0f26872c2ff705345b807d8353c8a3d46209dcommit | diff
add 8 CSRs for registers and predication each

each CSR contains 2 16-bit entries and is a CAM based on register as
key (5-bit) and target-register as value (6-bit) so that a 5-bit
RS1-3/RD can actually reach 64 actual registers, and *3-bit C instructions
can as well*
riscv/encoding.h diff | blob | history
Simple-V augmented version of spike