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(parent: ca39e49) | patch
Improving vpr output support.
authorTim 'mithro' Ansell <me@mith.ro>
Wed, 18 Apr 2018 23:48:05 +0000 (16:48 -0700)
committerTim 'mithro' Ansell <me@mith.ro>
Wed, 18 Apr 2018 23:55:12 +0000 (16:55 -0700)
commitd6bdefd2e93ad25fd63103d4b76a5573debc6d03
tree544397a34a4262465eb12b350469a9f63c0b19aatree
parentca39e493ba78e7a4eaf3f0876321f892cce20f65commit | diff
Improving vpr output support.

 * Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
techlibs/ice40/cells_map.v diff | blob | history
techlibs/ice40/synth_ice40.cc diff | blob | history
techlibs/xilinx/cells_map.v diff | blob | history
techlibs/xilinx/synth_xilinx.cc diff | blob | history