hdl.mem: add DummyPort, for testing and verification.
authorwhitequark <whitequark@whitequark.org>
Tue, 1 Jan 2019 03:08:10 +0000 (03:08 +0000)
committerwhitequark <whitequark@whitequark.org>
Tue, 1 Jan 2019 03:08:10 +0000 (03:08 +0000)
commitd78e6c155b6de72ab56f7cb123bc2b7cdb8f6b04
tree5479a730b84c605a150e35ae31e38d390addc879
parentae3c5834ed8484925d8bafe468530e789791c01e
hdl.mem: add DummyPort, for testing and verification.
nmigen/hdl/mem.py
nmigen/test/test_hdl_mem.py