X86: Implement the load machine status word instruction (LMSW).
authorGabe Black <gblack@eecs.umich.edu>
Sun, 19 Apr 2009 10:17:14 +0000 (03:17 -0700)
committerGabe Black <gblack@eecs.umich.edu>
Sun, 19 Apr 2009 10:17:14 +0000 (03:17 -0700)
commitd86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152
treeaaa3dfcc6a6284a2f2a0fc8e0d1b5a106c616d56
parentb4ad233c0c4aeb4f622a87ff6f7e5c4f072a2927
X86: Implement the load machine status word instruction (LMSW).
src/arch/x86/isa/decoder/two_byte_opcodes.isa
src/arch/x86/isa/insts/system/control_registers.py