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(parent: 314ec7b) | patch
i965: Do an end-of-pipe sync after flushes
authorJason Ekstrand <jason.ekstrand@intel.com>
Tue, 13 Jun 2017 17:31:41 +0000 (10:31 -0700)
committerJason Ekstrand <jason.ekstrand@intel.com>
Wed, 14 Jun 2017 22:11:42 +0000 (15:11 -0700)
commitd9261275cc1328d6a30e19b92db21df23adf7219
tree564a4a1f67389d80968d763699a3f2a63eb7e321tree
parent314ec7b46ffa1640c0d9448e7752c2d7f6c18734commit | diff
i965: Do an end-of-pipe sync after flushes

According to the docs, a simple CS stall is insufficient to ensure that
the memory from the flush is visible and an end-of-pipe sync is needed.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_pipe_control.c diff | blob | history