gen/fhdl/verilog: fix signed init values
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 12 Jan 2020 21:06:35 +0000 (22:06 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 12 Jan 2020 21:06:35 +0000 (22:06 +0100)
commitd92bd8ffaa9a9d1f3d51498c8e382f7041e69274
tree4963df486aef0197ab52ee89a05f0fe927a21901
parentff066a5e09389d4c6ae88321cd3763678f6f5550
gen/fhdl/verilog: fix signed init values
litex/gen/fhdl/verilog.py