add misaligned mem test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Dec 2022 13:20:56 +0000 (13:20 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:16 +0000 (19:51 +0100)
commitd9ad6b728bbc46efd4846d0670e8ae126381bc7a
tree693be208c8abd7a7fae4a1142b8d261661739d6e
parent6f35e16a30d21c7de8dcd499dcf5608b4547ab03
add misaligned mem test
src/openpower/decoder/isa/test_mem.py