Merge pull request #914 from YosysHQ/xc7srl
authorEddie Hung <eddieh@ece.ubc.ca>
Mon, 22 Apr 2019 20:31:30 +0000 (13:31 -0700)
committerGitHub <noreply@github.com>
Mon, 22 Apr 2019 20:31:30 +0000 (13:31 -0700)
commitd9daf09cf3aab202b6da058c5e959f6375a4541e
tree50f92b27b889077951583496266d214b5e0a30c7
parentbc98a463a433e5b1553b307301e67e641a148d3c
parentec88129a5cf510afc39ea12efa6059bed3eadfc3
Merge pull request #914 from YosysHQ/xc7srl

synth_xilinx to now infer SRL16E/SRLC32E