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freedreno/ir3: move binning-pass fixup for a6xx+
authorRob Clark <robdclark@gmail.com>
Fri, 12 Oct 2018 20:01:22 +0000 (16:01 -0400)
committerRob Clark <robdclark@gmail.com>
Wed, 17 Oct 2018 16:44:48 +0000 (12:44 -0400)
commitd9dbc9c21f17e4c86f8e366fbe225df39e3b7b59
tree8aac369382a6b6bdcaf229526f896ae0dd243cadtree
parent1a51c4a87ea9202af90ccb28bd697f0df753f587commit | diff
freedreno/ir3: move binning-pass fixup for a6xx+

Move this to after ir3_cp (which can add lowered immediates to the const
state) for a6xx+, to ensure the uniform state matches between binning
and vertex shaders.  This way we can emit just a single VS_CONST state-
group when we re-use single cmdstream for both binning and draw passes.

Signed-off-by: Rob Clark <robdclark@gmail.com>
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c diff | blob | history