Make O3CPU model independent of the ISA
authorKorey Sewell <ksewell@umich.edu>
Fri, 30 Jun 2006 23:52:08 +0000 (19:52 -0400)
committerKorey Sewell <ksewell@umich.edu>
Fri, 30 Jun 2006 23:52:08 +0000 (19:52 -0400)
commitd9ef772e8d43ebfd2a4bece76f33cc62d71258a6
treeb13b4f369dd77c3e0eefae25567fd69e8a986dc8
parent0fbecab797ffe7fc68e3a9af9fd0a21df37ec635
Make O3CPU model independent of the ISA

Use O3CPU when building instead of AlphaO3CPU.

I could use some better python magic in the cpu_models.py file!

AUTHORS:
    add middle initial
SConstruct:
    change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
    edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
    change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...

    Actually, some Python expertise could be used here. The 'env' variable is not
    passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use isa_specific.hh
src/sim/process.cc:
    only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
    alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
    move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
    Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
    include paths
src/cpu/o3/alpha/impl.hh:
    include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
    set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
    add O3CPU class
src/cpu/o3/SConscript:
    include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
    NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
    new home of AlphaTC
src/cpu/o3/isa_specific.hh:
    includes ISA specific files
src/cpu/o3/params.hh:
    base o3 params
src/cpu/o3/thread_context.hh:
    base o3 thread context
src/cpu/o3/thread_context_impl.hh:
    base o3 thead context impl

--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
46 files changed:
AUTHORS
SConstruct
src/cpu/SConscript
src/cpu/cpu_models.py
src/cpu/o3/SConscript [new file with mode: 0755]
src/cpu/o3/alpha/cpu.cc [new file with mode: 0644]
src/cpu/o3/alpha/cpu.hh [new file with mode: 0644]
src/cpu/o3/alpha/cpu_builder.cc [new file with mode: 0644]
src/cpu/o3/alpha/cpu_impl.hh [new file with mode: 0644]
src/cpu/o3/alpha/dyn_inst.cc [new file with mode: 0644]
src/cpu/o3/alpha/dyn_inst.hh [new file with mode: 0644]
src/cpu/o3/alpha/dyn_inst_impl.hh [new file with mode: 0644]
src/cpu/o3/alpha/impl.hh [new file with mode: 0644]
src/cpu/o3/alpha/params.hh [new file with mode: 0644]
src/cpu/o3/alpha/thread_context.cc [new file with mode: 0755]
src/cpu/o3/alpha/thread_context.hh [new file with mode: 0644]
src/cpu/o3/alpha_cpu.cc [deleted file]
src/cpu/o3/alpha_cpu.hh [deleted file]
src/cpu/o3/alpha_cpu_builder.cc [deleted file]
src/cpu/o3/alpha_cpu_impl.hh [deleted file]
src/cpu/o3/alpha_dyn_inst.cc [deleted file]
src/cpu/o3/alpha_dyn_inst.hh [deleted file]
src/cpu/o3/alpha_dyn_inst_impl.hh [deleted file]
src/cpu/o3/alpha_impl.hh [deleted file]
src/cpu/o3/alpha_params.hh [deleted file]
src/cpu/o3/base_dyn_inst.cc
src/cpu/o3/bpred_unit.cc
src/cpu/o3/commit.cc
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/decode.cc
src/cpu/o3/fetch.cc
src/cpu/o3/iew.cc
src/cpu/o3/inst_queue.cc
src/cpu/o3/isa_specific.hh [new file with mode: 0755]
src/cpu/o3/lsq.cc
src/cpu/o3/lsq_unit.cc
src/cpu/o3/mem_dep_unit.cc
src/cpu/o3/params.hh [new file with mode: 0755]
src/cpu/o3/rename.cc
src/cpu/o3/rob.cc
src/cpu/o3/thread_context.hh [new file with mode: 0755]
src/cpu/o3/thread_context_impl.hh [new file with mode: 0755]
src/python/m5/objects/AlphaO3CPU.py [deleted file]
src/python/m5/objects/O3CPU.py [new file with mode: 0644]
src/sim/process.cc