git.libre-soc.org Git - gem5.git/commit

author	Gabe Black <gblack@eecs.umich.edu>
	Sun, 12 Oct 2008 16:09:56 +0000 (09:09 -0700)
committer	Gabe Black <gblack@eecs.umich.edu>
	Sun, 12 Oct 2008 16:09:56 +0000 (09:09 -0700)
commit	d9f9c967fbe651e09d444e460a9b1c5a450b1cd2
tree	ba705f0a9f18e5c96fbec3b4f3691761235be7e2	tree
parent	c4f1cc3b482311f878be44259125c9a5b90c0569	commit \| diff

Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.

28 files changed:

src/arch/alpha/AlphaInterrupts.py	[new file with mode: 0644]	blob
src/arch/alpha/SConscript		diff \| blob \| history
src/arch/alpha/interrupts.cc	[new file with mode: 0644]	blob
src/arch/alpha/interrupts.hh		diff \| blob \| history
src/arch/mips/MipsInterrupts.py	[new file with mode: 0644]	blob
src/arch/mips/SConscript		diff \| blob \| history
src/arch/sparc/SConscript		diff \| blob \| history
src/arch/sparc/SparcInterrupts.py	[new file with mode: 0644]	blob
src/arch/sparc/interrupts.cc	[new file with mode: 0644]	blob
src/arch/sparc/interrupts.hh		diff \| blob \| history
src/arch/x86/SConscript		diff \| blob \| history
src/arch/x86/X86LocalApic.py	[new file with mode: 0644]	blob
src/arch/x86/apicregs.hh	[new file with mode: 0644]	blob
src/arch/x86/interrupts.cc	[new file with mode: 0644]	blob
src/arch/x86/interrupts.hh		diff \| blob \| history
src/arch/x86/miscregfile.cc		diff \| blob \| history
src/arch/x86/miscregfile.hh		diff \| blob \| history
src/arch/x86/miscregs.hh		diff \| blob \| history
src/arch/x86/mmaped_ipr.hh		diff \| blob \| history
src/arch/x86/regfile.cc		diff \| blob \| history
src/arch/x86/tlb.cc		diff \| blob \| history
src/arch/x86/utility.cc		diff \| blob \| history
src/cpu/BaseCPU.py		diff \| blob \| history
src/cpu/base.cc		diff \| blob \| history
src/cpu/base.hh		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/ozone/cpu_impl.hh		diff \| blob \| history
src/cpu/simple/base.cc		diff \| blob \| history