add stream, fix CPUs and more imports. simple target boots on ppro.
authorSebastien Bourdeauducq <sb@m-labs.hk>
Sat, 26 Sep 2015 08:44:06 +0000 (16:44 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Sat, 26 Sep 2015 08:44:21 +0000 (16:44 +0800)
commitda425d1bcb62bd2b5abcbb7ef32df9b9621d2280
tree8d917a1c4fa161ccfc576c4599223a537d4ffe97
parent75ef2f9004346e21da879241471b3f5b7782c195
add stream, fix CPUs and more imports. simple target boots on ppro.
12 files changed:
make.py
misoc/cores/lm32/__init__.py [new file with mode: 0644]
misoc/cores/lm32/core.py
misoc/cores/lm32/verilog/submodule [new submodule]
misoc/cores/mor1kx/__init__.py
misoc/cores/mor1kx/core.py
misoc/cores/mor1kx/verilog [new submodule]
misoc/cores/uart/core.py
misoc/integration/soc_core.py
misoc/interconnect/csr_bus.py
misoc/interconnect/stream.py [new file with mode: 0644]
software/common.mak