author | Sebastien Bourdeauducq <sb@m-labs.hk> | |
Sat, 26 Sep 2015 08:44:06 +0000 (16:44 +0800) | ||
committer | Sebastien Bourdeauducq <sb@m-labs.hk> | |
Sat, 26 Sep 2015 08:44:21 +0000 (16:44 +0800) | ||
commit | da425d1bcb62bd2b5abcbb7ef32df9b9621d2280 | |
tree | 8d917a1c4fa161ccfc576c4599223a537d4ffe97 | tree |
parent | 75ef2f9004346e21da879241471b3f5b7782c195 | commit | diff |
make.py | diff | blob | history | |
misoc/cores/lm32/__init__.py | [new file with mode: 0644] | blob |
misoc/cores/lm32/core.py | diff | blob | history | |
misoc/cores/lm32/verilog/submodule | [new submodule] | blob |
misoc/cores/mor1kx/__init__.py | diff | blob | history | |
misoc/cores/mor1kx/core.py | diff | blob | history | |
misoc/cores/mor1kx/verilog | [new submodule] | blob |
misoc/cores/uart/core.py | diff | blob | history | |
misoc/integration/soc_core.py | diff | blob | history | |
misoc/interconnect/csr_bus.py | diff | blob | history | |
misoc/interconnect/stream.py | [new file with mode: 0644] | blob |
software/common.mak | diff | blob | history |