Merge pull request #1098 from YosysHQ/xaig
authorEddie Hung <eddie@fpgeh.com>
Fri, 28 Jun 2019 17:59:03 +0000 (10:59 -0700)
committerGitHub <noreply@github.com>
Fri, 28 Jun 2019 17:59:03 +0000 (10:59 -0700)
commitda5f83039527bf50af001671744f351988c3261a
tree5af77e4b5c61a5d31b18cc807818d884b6884ec1
parent74945dd738fca316f319771426646c4da327f662
parent38d8806bd74b9bb448c7488ec571e197fe2f96d6
Merge pull request #1098 from YosysHQ/xaig

"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
Makefile