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(parent: c98bd9f) | patch
liteusb: add simple example design with wishbone bridge and software to control it
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 2 May 2015 15:39:22 +0000 (17:39 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 2 May 2015 16:21:18 +0000 (18:21 +0200)
commitda711ad5f12c2186d2ace69d717f6a8b8bee19a2
tree58f910855917df6fe56956a458ed86e747ad1726tree
parentc98bd9fd7955daf77ed55602c2f9b5392ce8ce3ccommit | diff
liteusb: add simple example design with wishbone bridge and software to control it
misoclib/com/liteusb/README diff | blob | history
misoclib/com/liteusb/example_designs/build/.keep_me [new file with mode: 0644] blob
misoclib/com/liteusb/example_designs/make.py [new file with mode: 0644] blob
misoclib/com/liteusb/example_designs/targets/__init__.py [new file with mode: 0644] blob
misoclib/com/liteusb/example_designs/targets/simple.py [new file with mode: 0644] blob
misoclib/com/liteusb/example_designs/test/Makefile [new file with mode: 0644] blob
misoclib/com/liteusb/example_designs/test/make.py [new file with mode: 0644] blob
misoclib/com/liteusb/example_designs/test/test_regs.py [new file with mode: 0644] blob
misoclib/com/liteusb/frontend/__init__.py [new file with mode: 0644] blob
misoclib/com/liteusb/software/wishbone.py diff | blob | history