projects / gem5.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 7f9c984) | patch
cpu: O3 switchFreeList checking VecElems instead of FloatRegs
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 29 Mar 2019 13:02:05 +0000 (13:02 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 10 Apr 2019 08:41:53 +0000 (08:41 +0000)
commitdaa9dcbc0c3fe4e5014855c8b31f1cfeb5f0af91
tree65b0e6feced44355aa991fa47ab892a1d5e2f50ftree
parent7f9c98472c97f8f71f71c7386496af67fc886d03commit | diff
cpu: O3 switchFreeList checking VecElems instead of FloatRegs

Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.

Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
src/cpu/o3/rename_map.cc diff | blob | history