mem: Add NVM interface
authorWendy Elsasser <wendy.elsasser@arm.com>
Wed, 1 Apr 2020 17:39:42 +0000 (12:39 -0500)
committerJason Lowe-Power <power.jg@gmail.com>
Tue, 8 Sep 2020 16:38:47 +0000 (16:38 +0000)
commitdab7c78ecad256fc7a721dfa7820d7f357eb8711
treee15220d1fc94eb045798c0cf022142a2d52267e3
parent4acc419b6fa5ea7bbc1cf128e75be1cc263557b0
mem: Add NVM interface

Add NVM interface to memory controller.

This can be used with or instead of the existing
DRAM interface. Therefore, a single controller can interface
to either DRAM or NVM, or both.

Specifically, a memory channel can be configured as:
- Memory controller interfacing to DRAM only
- Memory controller interfacing to NVM only
- Memory controller interfacing to both DRAM and NVM

How data is placed or migrated between media types is outside
of the scope of this change.

The NVM interface incorporates new static delay parameters
for read and write completion. The interface defines a 2
stage read to manage non-deterministic read delays while
enabling deterministic data transfer, similar to NVDIMM-P.
The NVM interface also includes parameters to define
read and write buffers on the media side (on-DIMM). These are
utilized to quickly offload commands and write data, mitigating
the effects of lower latency and bandwidth media characteristics.

Change-Id: I6b22ddb495877f88d161f0bd74ade32cc8fdcbcc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29027
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
20 files changed:
configs/common/MemConfig.py
configs/nvm/sweep.py [new file with mode: 0644]
configs/nvm/sweep_hybrid.py [new file with mode: 0644]
configs/ruby/Ruby.py
src/cpu/testers/traffic_gen/PyTrafficGen.py
src/cpu/testers/traffic_gen/SConscript
src/cpu/testers/traffic_gen/base.cc
src/cpu/testers/traffic_gen/base.hh
src/cpu/testers/traffic_gen/hybrid_gen.cc [new file with mode: 0644]
src/cpu/testers/traffic_gen/hybrid_gen.hh [new file with mode: 0644]
src/cpu/testers/traffic_gen/nvm_gen.cc [new file with mode: 0644]
src/cpu/testers/traffic_gen/nvm_gen.hh [new file with mode: 0644]
src/cpu/testers/traffic_gen/traffic_gen.cc
src/mem/DRAMCtrl.py
src/mem/DRAMInterface.py
src/mem/MemInterface.py [new file with mode: 0644]
src/mem/NVMInterface.py [new file with mode: 0644]
src/mem/SConscript
src/mem/dram_ctrl.cc
src/mem/dram_ctrl.hh