Add testbench for SoC simulation
authorJean THOMAS <git0@pub.jeanthomas.me>
Fri, 26 Jun 2020 14:41:55 +0000 (16:41 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Fri, 26 Jun 2020 14:41:55 +0000 (16:41 +0200)
commitdaea9f75e1328fa140757af76cd5e32abec45379
tree31fdda859e61f15f77accd975a57bff19e63fb74
parentf869eb97a9fdb7ef9d086d295782f3e4304e6a7f
Add testbench for SoC simulation
gram/simulation/simsoctb.v [new file with mode: 0644]