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(parent: 9c5a0f3) | patch
add RC1 support to ISACaller.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 24 Sep 2022 16:17:55 +0000 (17:17 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 24 Sep 2022 16:17:55 +0000 (17:17 +0100)
commitdb6d324297e415eb2358df6c31d193dae59dc256
treeba01a2498bcb9c27d6df0bfd69b520be1e302666tree
parent9c5a0f34f35a3f8f803a425b28160365d42dfcbbcommit | diff
add RC1 support to ISACaller.
this involves:
* reading Rc=0 and substituting RC1 in its place OR
* for non-Rc instructions just putting RC1 in place of Rc
* reading VLi flag and adding it to srcstep to put into VL on ffirst hit
* setting the cr-bit to test to EQ in RC1 mode
src/openpower/consts.py diff | blob | history
src/openpower/decoder/isa/caller.py diff | blob | history
src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py diff | blob | history
src/openpower/decoder/power_decoder2.py diff | blob | history
src/openpower/decoder/power_svp64_rm.py diff | blob | history