soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 1 Jan 2020 12:24:06 +0000 (13:24 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 1 Jan 2020 12:24:06 +0000 (13:24 +0100)
commitdb7a48c05dec0f2e737dc9ee6726da20d70db514
tree5d6865384b77548e43a0f680b2f9295e368ac3cc
parentcaacc411034974a55d8bfa257ccd1706c6aab0e6
soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL
litex/soc/cores/clock.py