Enabled AST/Verilog front-end optimizations per default
authorClifford Wolf <clifford@clifford.at>
Mon, 10 Jun 2013 11:19:04 +0000 (13:19 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 10 Jun 2013 11:19:04 +0000 (13:19 +0200)
commitdb98a18edb02a5c3a0c3f26efec0e01f8232790a
tree2f1d2758fe775d7d39b0a09561525681f9c6452f
parentaf79b4bd9827ec0c8aff284a44e861ab0d0efff1
Enabled AST/Verilog front-end optimizations per default
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
frontends/verilog/verilog_frontend.cc