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(parent: 637a02e) | patch
Allow $size and $bits in verilog mode, actually check test case
authorClifford Wolf <clifford@clifford.at>
Fri, 29 Sep 2017 09:56:43 +0000 (11:56 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 29 Sep 2017 09:56:43 +0000 (11:56 +0200)
commitdbfd8460a9f1d24d1c8893dfae7dd272d17a7b6f
tree7afbacc238f153323f425f39987e0520e0b844eetree
parent637a02eb5cf8ef09a7fb02af31d6149a31460d0fcommit | diff
Allow $size and $bits in verilog mode, actually check test case
frontends/ast/simplify.cc diff | blob | history
tests/sat/sizebits.sv [new file with mode: 0644] blob
tests/sat/sizebits.ys [new file with mode: 0644] blob
tests/simple/functions01.sv [deleted file] blob | history