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(parent: 0e4c343) | patch
arch-arm: ISV bit in DataAbort should check for translation stage
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Fri, 6 Sep 2019 13:44:47 +0000 (14:44 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 18 Sep 2019 13:30:01 +0000 (13:30 +0000)
commitdc70987e470d66f584e0ddf606e9f07da994ba75
tree4c79dd20570f9378b8835b4c52335139fd95fb79tree
parent0e4c3437fdfb20e0f0d590e0d0abe32fc8393b3ccommit | diff
arch-arm: ISV bit in DataAbort should check for translation stage

According to the ESR spec, the ISV bit is set to 1 only for stage 2
aborts.

Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/faults.cc diff | blob | history