projects / microwatt.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b70a617) | patch
Extend LiteDRAM VHDL wrapper to allow more than one clock line
authorRaptor Engineering Development Team <support@raptorengineering.com>
Tue, 22 Feb 2022 18:35:30 +0000 (12:35 -0600)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Tue, 22 Feb 2022 21:03:48 +0000 (15:03 -0600)
commitddc1cc062caed16cbc7fc948e973f4ad72b486f9
tree67d01ff6ab98844cb78dbcc4750b27e6a461c1detree
parentb70a6177f68880cc3724c444d3771d24d7be36efcommit | diff
Extend LiteDRAM VHDL wrapper to allow more than one clock line

This is necessary for the upcoming Arctic Tern system enablement
core_dram_tb.vhdl diff | blob | history
dram_tb.vhdl diff | blob | history
fpga/top-acorn-cle-215.vhdl diff | blob | history
fpga/top-arty.vhdl diff | blob | history
fpga/top-genesys2.vhdl diff | blob | history
fpga/top-nexys-video.vhdl diff | blob | history
litedram/extras/litedram-wrapper-l2.vhdl diff | blob | history
litedram/extras/sim_litedram.vhdl diff | blob | history