Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all...
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 25 Apr 2013 18:18:45 +0000 (20:18 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 25 Apr 2013 18:18:45 +0000 (20:18 +0200)
commitde76faf7577c23fba99365afda5377237f4b6f20
tree5ee0b3c47b9531c41ce4338a3c6e0e84225586b2
parent4ff1175dcf504968706abe3fc8a09c1d2e701bca
Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
build.py