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(parent: 8f6a40b) | patch
whilst IOpads and PLLs were driving from dramsync, they were *not*
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 10:34:48 +0000 (11:34 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 10:34:48 +0000 (11:34 +0100)
commitdedba0951797896c4f6c44238ebffc7e4472f0f2
tree8054de3fe31cffd03897cb712d468bbf99fa0c17tree
parent8f6a40bb418e346a78af5a83a5bc20f0ed538d57commit | diff
whilst IOpads and PLLs were driving from dramsync, they were *not*
driving the 4x from dramsync2x, but from sync2x instead.
which is completely wrong when trying to do asynchronous DRAM PHY
for when synchronous is done (the default right now) this requires a matching
            drs = DomainRenamer({"sync": "dramsync",
                                 "sync2x": "dramsync2x"})
gram/phy/ecp5ddrphy.py diff | blob | history