i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().
authorKenneth Graunke <kenneth@whitecape.org>
Tue, 29 Aug 2017 05:00:12 +0000 (22:00 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Wed, 30 Aug 2017 23:59:22 +0000 (16:59 -0700)
commitdf8f4bfc02d631412632a8bef537a2e4cec4945b
tree94ec18573b43aa3870a5bff1a9d826ac3c787734
parent225425111fee082e3be14c22c256314b85724ef8
i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().

Although we're phasing out brw_emit_mi_flush(), we still use it in some
places in order to "flush everything".  In a number of those places, we
write data to a buffer that we may then bind as an image surface, SSBO,
or atomic buffer.  Those usages require us to flush the data cache.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
src/mesa/drivers/dri/i965/brw_pipe_control.c