Added Verilog $rtoi and $itor support
authorClifford Wolf <clifford@clifford.at>
Tue, 3 Jan 2017 16:40:58 +0000 (17:40 +0100)
committerClifford Wolf <clifford@clifford.at>
Tue, 3 Jan 2017 16:40:58 +0000 (17:40 +0100)
commitdfb461fe5213ec649f384f1e1dbd6d58d5763910
tree8866cc6207615910b8233b706812e5e0f03ca08c
parent81bb952e5d2125f3e0700a8a61d2d33297e8b710
Added Verilog $rtoi and $itor support
frontends/ast/simplify.cc