arch-power: Fix fixed-point load and store instructions
This fixes the following load and store instructions as a result
of the change in register widths:
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic (lwa)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes disassembly generation for all of the above.
Change-Id: I1a25cdb5ffe86145b7ffcf2c2bd7b27048a415d2
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>