Use more conservative fences on RISC-V

Use more conservative fences on RISC-V

The RISC-V memory model is still in the process of being formally
specified, so for now we're going to be safe and add the I/O bits to
userspace fences because there's no way to know if userspace is touching
memory-mapped I/O regions at compile time.

This will have no impact on existing microarchitecutres because they
treat all fences conservatively.

gcc/ChangeLog:

2017-03-17  Palmer Dabbelt  <palmer@dabbelt.com>

        * config/riscv/riscv.c (riscv_print_operand): Use "fence
        iorw,ow".
        * config/riscv/sync.mc (mem_thread_fence_1): Use "fence
        iorw,iorw".

From-SVN: r246282