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(parent: 70e3280) | patch
sim: make sure replaced memory signals are always in VCD signal set
authorSebastien Bourdeauducq <sb@m-labs.hk>
Mon, 5 Oct 2015 04:24:32 +0000 (12:24 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Mon, 5 Oct 2015 04:24:32 +0000 (12:24 +0800)
commite0899c1424ccc04ad161fbe9b7107c7d6373d98f
tree6849364a482830561a4307ecfcf406dcc7edbbc0tree
parent70e328057974f96e22ac3c9237be4e747512462fcommit | diff
sim: make sure replaced memory signals are always in VCD signal set
migen/sim/core.py diff | blob | history