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(parent: 362a803) | patch
Fix DSP48E1 timing by breaking P path if MREG or PREG
authorEddie Hung <eddie@fpgeh.com>
Fri, 20 Sep 2019 01:59:28 +0000 (18:59 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 20 Sep 2019 01:59:28 +0000 (18:59 -0700)
commite09f80479e6d16cf95c26e406bf06d81b94231f4
tree44e0ac0df9cfb0801bf919a75d2e70a61bbdb7d4tree
parent362a803779ac1a8a3af1e4991b80b0c4c71e02ffcommit | diff
Fix DSP48E1 timing by breaking P path if MREG or PREG
techlibs/xilinx/abc_map.v diff | blob | history
techlibs/xilinx/abc_model.v diff | blob | history
techlibs/xilinx/abc_unmap.v diff | blob | history
techlibs/xilinx/abc_xc7.box diff | blob | history