wishbone: add extracting module signals to the top
authorJan Kowalewski <jkowalewski@antmicro.com>
Thu, 13 Feb 2020 15:41:11 +0000 (16:41 +0100)
committerPiotr Binkowski <pbinkowski@antmicro.com>
Fri, 21 Feb 2020 10:20:32 +0000 (11:20 +0100)
commite0bcb57d3d0b905502502733ffd9b9531d2cc8df
treed533d55a20f761765745409f7c4310e3e0a23334
parent485934edc9c1e123e3e39911b910b51aa3196b19
wishbone: add extracting module signals to the top
litex/soc/interconnect/wishbone.py