mem-cache: Fix MSHR whole line write tracking
authorNikos Nikoleris <nikos.nikoleris@arm.com>
Tue, 25 Jun 2019 12:55:42 +0000 (13:55 +0100)
committerNikos Nikoleris <nikos.nikoleris@arm.com>
Tue, 29 Oct 2019 09:41:41 +0000 (09:41 +0000)
commite0de180ee4eb3316d2dd0d20320f2a1b310101bc
tree756c095d7d55f2eadb97f34bd1932f6c53ee0378
parentaf48fb9373a16deecb04476fdcc7e5b7ffa3a63a
mem-cache: Fix MSHR whole line write tracking

The MSHR keeps track of outstanding writes and services them as a
whole line write whenever possible. To do this the outstanding writes
have to be compatible (e.g., not strictly ordered). Prior to this
change, due to this tracking mechanism, the MSHR would not service a
WriteLineReq with flags that do not allow merging as a full line write
even if it was the first target triggering an assertion. This
changeset fixes this bug.

Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
src/mem/cache/mshr.hh