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(parent: 5998c10) | patch
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
authorClifford Wolf <clifford@clifford.at>
Fri, 18 Oct 2013 10:13:34 +0000 (12:13 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 18 Oct 2013 10:13:34 +0000 (12:13 +0200)
commite0f693cbb09ac1a952fc49e507daefa30169bd35
treec3635ce8b3e472a48d74544d3fc3dd79b1ff46eatree
parent5998c101a46c5121db0fa73b3af1f180a73d7fd5commit | diff
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
backends/verilog/verilog_backend.cc diff | blob | history
kernel/celltypes.h diff | blob | history
techlibs/common/stdcells_sim.v diff | blob | history